Summary: This tutorial will provide an overview of advanced interconnect technologies, including dielectric materials, patterning, metallization, CMP, and packaging. New processes will be discussed, such as ultra-low K dielectrics, air-gap structures, low-damage patterning methods, thin barrier and seed layers, refractory metal capping layers, and novel CMP techniques. The effect of these processes on performance and reliability will be briefly described.

Summary: The cellular wave computer architecture, based on the CNN universal machine principle, has been implemented recently in many different physical forms. The mixed mode CMOS, the emulated digital (cell wise or as aggregated arrays), FPGA, DSP, as well as optical implementations are the main examples. In many cases, the sensory array is integrated as well.

This course will begin with an introduction which will provide a historical overview, mind inspired and brain inspired computing models, the role of spatial address of a processor, new directions and products in computing The technology scenario. Other topics that will be addressed include:

*The Cellular Wave Computer
*The Cell Processors
*The Biology Relevance
*The Algorithmic Scenario
*Beyond Boolean logic

Summary: Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this tutorial examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the active power of a processor chip will increase precipitously below the 0.1-µm or 100-nm technology generation. To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented. It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile. Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm.

Summary: This course discusses on-chip wires, how to model them, what are their problems (and their advantages) and some solutions. Topics that will be covered include: Wire characteristics and how they determine performance; Wires under technology scaling; and Methods to improve wire performance.

Summary: The concept of the 'Analog Front End' (AFE), which is the interface to the real world in most IC-system chips, is first introduced. The course then focuses on active-RC filters which constitute an essential part of most AFEs. The formulation of filter specifications and the basic ideas associated with classical filter approximation theory are then briefly reviewed. Some key points of classical network theory, as needed for the understanding of inductorless filter design, are then briefly recalled. This is followed by some basic concepts of signal-flow graph theory, which permit the transition from transfer function (resulting from approximation theory) to circuit topology. After the review of these introductory and basic concepts, the stage is set to consider some of the most important and established active-RC filter-design techniques. Examples are given for the conversion of classical LCR filter structures into inductorless active-RC filter circuits that are amenable to IC chip design. The examples are taken from typical modern communication systems. Finally, filters designed using the design techniques covered in the course are compared in terms of practical performance criteria such as thermal output noise, sensitivity to component tolerances, and tunablity.

Summary: The objective of this course is to provide a state of the art review of phase locked loop circuits and applications from a design and development perspective. Intended for RF and Microwave Engineers, the course details out the design and development of phase locked loop circuits. Topics include PLL basics, VCOs, phase detectors, open and close loop characterization, loop filter design, and phase noise concepts. Examples will be given to a variety of problems relevant to the design of phase locked loops.

Summary: This is a hot topic due to immediate demand from industry. However, the key design issues are often ignored, in particular by the students. In this course, these issues will be highlighted from an application point of view. The theoretical analysis is also given to help students understand the broadband radiation behavior well. The following is the abstract of the course.
The research and development of ultra-wideband (UWB) technology has greatly spurred the design of small broadband antennas. The requirements for the UWB antennas include consistent impedance and radiation performance over an ultra-wide bandwidth of 3.1-4.8GHz/6-10.6GHz/3.1-10.6GHz. The miniaturization of the antennas becomes the most critical design challenges in commercial UWB systems such as high-speed wireless USB dongles. This course reviews the development of the small UWB antennas. The key design issues of the UWB antennas such as planar printed UWB antennas are highlighted. The new techniques to reduce the effect of ground plane on the antenna performance, further miniaturize antenna, co-design antenna with RF filters are elaborated. The latest applications of small printed antennas in wireless UWB systems are described in brief.

Summary: The role of Radio-Frequency (RF) Power Amplifiers (PAs) in today's and tomorrow's consumer and state-of-the-art electronics is crucial, catering to the stringent performance (i.e., linearity and output power) and real-estate (i.e., size) requirements of portable systems and the power limitations of battery-powered applications. Key to the success of any portable device is battery life (or runtime), and PAs can be a significant and detrimental load in this regard, especially because they capture a significant portion of the total power budget and they characteristically have poor power efficiencies. This course will address the advent of dynamically adaptive biasing schemes in PA applications to increase power efficiencies, which is generally done by essentially transforming and redefining the operating environment of the PA for maximum performance at optimum power levels, and consequently prolonging battery life. After completing this course you should be able to develop an understanding of dynamically adaptive biasing schemes in PA applications.

Summary: This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to activate latent defects and screen out those chips that cannot meet product specifications for performance, power and operating margins. The advent of degraded VLSI circuit operating margins due to the activated defects as well as reliability mechanisms such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and others will be discussed. How these failing circuits can then manifest themselves in observed product failures will also be discussed. After completing this course you should be able to develop an understanding of: Reliability and today's VLSI chips; Reliability and VLSI design; VLSI circuits; Circuit reliability mechanisms.

Summary: Various RF bands, standards, modulation schemes, duplex mechanisms and signal bandwidths needed for the mobile terminal call for a highly adaptable and reconfigurable RF receiver. The biggest bottleneck in achieving this goal lies with the RF pre-select filter at the antenna, which is band specific and creates a bottleneck in being able to share the hardware. Solving this "multi-band" programmability is the biggest challenge in achieving a RF Receiver for software defined radio. A few of the possible architectures and their limitations are presented. However, designing a "multi-mode" RF receiver for a given RF band with highly reconfigurable performance is an achievable goal. A WCDMA/EDGE receiver without inter-stage SAW filter in 90nm digital CMOS is used as an example in illustrating the architecture, circuit and system considerations for such a receiver.

Summary: A design methodology for sizing and determining delays in logic paths will be developed that will be used throughout the design cycle. One of the key items in sizing and optimizing the logic path is called fanout which will be the main focuses of this tutorial. We will first determine what fanout is and how it relates to the gain (output capacitance vs. input capacitance) of an inverter and a complete logic path. Then, a delay equation for calculating the delay through any logic path based on fanout will be created to aid in quickly calculating the initial timing and sizing of the logic gates. Timing and sizing calculations will always be related to an inverter, so we will review how to convert a NAND and NOR gate drive strength to an equivalent inverter to be used in the delay equation.

A key question that will always arise throughout a design will be: what is the optimum fanout when we have a very small initial stage in a logic path that must eventually drive a large capacitance? In another words, how many gain stages should we use and what size should each stage be. To answer this, we will create a graph that will tell us the optimum fanout that we should always use and thus standardize the delay per stage. Standardizing fanout will eliminate many variations within our design and allow for all logic paths to track over process, temperature and voltage variations. This is a very important design methodology in improving the quality of our design and helping to insure that it works the first time.

Summary: Part 2 will expand the analysis of delay and fanout to include the additional parasitic capacitance load that occurs from layout. A standardized method for converting capacitance to equivalent gate size will be presented, and the examples from Part 1 will be reworked to include parasitic capacitance. It is imperative that there be a good understanding of how layout causes parasitic capacitance which can greatly affect the performance and functionality of a design. We will evaluate this by first reviewing the basics of layout with substantial focus on the metal interconnect layers and the types of capacitance the various structures create. Finally, a simulation methodology will be presented for incorporating the actual extracted layout into SPICE for an accurate analysis of the design.

Summary: This tutorial would introduce important issues in preparing, designing, and developing a product including: Systems Engineering – Process, design, and development; Architecture – Hardware, Software, Tradeoffs; Interface choices; Reliability versus fault tolerance; Review and Testing - Debugging, inspections, integration, validation, verification; Documentation; The Human Interface - User-centered design, elements of successful interfaces; Packaging - Its influence, environmental issues, wiring and assembly issues; Power - Types of converters and distribution; Cooling - Mechanisms, types of heat transfer, and tradeoffs; Problems - types of problems, failure, remedies, integrity.

Summary: This course will provide an overview of memristors. The course will explain what a memristor is, as well as what makes it the fourth circuit element. You will be presented with specific topics including:

* What are its fingerprints?

* What makes it a non-volatile memory?

* How do you write/read a memory state?

* Why are most non-volatile devices reported so far in the nano literatures memristive?

* Why are memristive phenomena ubiquitous?

* Why is a light bulb memristive?

* What aspect of the neuron is memristive?

* What aspect of the Josephson junction is memristive?

Summary: The course introduces multilayer perceptrons in a self-contained way by providing motivations, architectural issues, and the main ideas behind the Backpropagation learning algorithm. In addition, the course shows how multilayer perceptrons can be successfully used in real-world applications

Summary: Variability is a reality in nanometer semiconductor processes. This course will cover the sources of systematic and random variations of transistors and their surrounding interconnects. Included in the variability discussion will be withinchip variability, across-wafer variability, across-device variability, and device mismatch. The resulting impact upon an individual circuit’s functionality and timing will be explored. Analytical approaches will be shown for examining the variability’s impact upon leakage power, dynamic power, and circuit functionality of static and dynamic circuits, SRAM arrays, and PLLs. Techniques will include Monte-Carlo analysis, vector analysis, and statistical timing analysis.

Summary: This course will begin by outlining approaching limits of conventional CMOS technology. New architectural requirements and paradigms for future nanoelectronics will be described. .Top-down. and .bottom-up. manufacturing paradigms, particularly self-assembly of organic monolayers will be discussed. Theoretical and experimental realizations of molecular-scale electronic switches will be described. This course will also show nanoscale memory and logic circuits built with these materials and methods and will discuss potential nanoscale chemical and biological sensors built with these materials and methods.

Summary: This is a two-part course. Part 2 titled, "Molecular Electronics-II: Molecular Electronic Device Fabrication and Characterization" will: Discuss the advantages of molecular electronic devices and present experimental proof of concepts; Describe the formation of molecular junctions, the central component of molecular electronic devices; Describe the design and fabrication approaches for some of the most successful molecular electronic device prototypes; Present electrical characterization approaches and challenges; Discuss non-device based electrical screening approaches; Present the current status and outlook for molecular electronic devices.

Summary: This is a 2-part course. This tutorial is an introduction to the emerging opportunities in novel nanoscale devices and fabrication techniques, with particular emphasis on the implications for circuit and system designers. Topics covered include: fundamentals of device physics and materials science at the nanoscale, the ITRS Emerging Research Devices (memory & logic), nanotubes, nanowires, and nanoparticles, molecular devices, nanofabrication techniques and their impact on device layout. An assessment of the level of maturity for the proposed devices will be given. Part I provides an introduction, outlines key challenges, and covers ITRS emerging research devices, nanotubes and nanowires.

Summary: This is a 2-part course. This tutorial is an introduction to the emerging opportunities in novel nanoscale devices and fabrication techniques, with particular emphasis on the implications for circuit and system designers. Topics covered include: fundamentals of device physics and materials science at the nanoscale, the ITRS Emerging Research Devices (memory & logic), nanotubes, nanowires, and nanoparticles, molecular devices, nanofabrication techniques and their impact on device layout. An assessment of the level of maturity for the proposed devices will be given. Part II covers molecular electronics, emerging research memory devices, resistivity switching, nano for Si technology, and layout restrictions.

Summary: This course provides an introductory, tutorial-type overview of key optoelectronic devices for optical communication systems, specifically, semiconductor lasers, photodetectors, optical modulators, and some WDM components. The course covers a broad range of devices with an emphasis on fundamental device physics and operating principles. Important performance parameters including design tradeoffs will also be discussed. The laser section will discuss applications and the types of lasers that are utilized for specific systems. Topics include multiple quantum well lasers, distributed feedback lasers, wavelength tunable lasers and vertical cavity surface emitting lasers. Photodetector topics will cover wide-bandwidth PINs and avalanche photodiodes as well as receivers with optical preamplification. State-of-the-art integrated receiver circuits will also be discussed. In the modulator section Mach-Zehnder interferometers, and quantum-confined-Stark-effect devices will be covered. There will be a brief description of recent developments in optical switching using MEMs technology.

Summary: The course will explain the theory underlying OFET operation, discuss practical fabrication strategies in use and underdevelopment, and discuss characterization and simulation of these devices, as well as some simple circuit implications considering their performance strengths and limitations.

Summary: This tutorial provides a practical introduction to PLL design for clock synthesis. The twin goals of the tutorial are to provide practical advice on solving real-world PLL problems and to help develop an intuitive feel for PLL theory in order to prevent common design mistakes. This tutorial includes basic feedback loop theory and common circuit implementations, with emphasis on typical problem spots. It also focuses on design for test and debug, an important but often overlooked topic. In 1988 I joined Integrated CMOS Systems as a circuit/device engineer, working on device modeling and characterization as well as cell library automation.

Summary: In typical radio-frequency (RF) front-end circuits, the passive components outnumber the active devices. They occupy a major fraction of the total circuit area, and their low quality factor (Q) limits the circuit performance. Furthermore, these (intended) passive components can easily be perturbed by the interconnects feeding into them and coupled together by the (unintended) magnetic fields around those interconnects, or by (unintended) capacitive currents through the silicon substrate. One therefore needs to cope with both the optimization of the passive components, as far as Q and chip area consumption go, and the minimization of the crosstalk effects. This tutorial illustrates the design principles that lead to optimized integrated passive components on the basis of maximum Q and optimum RF isolation. Taking the well-established hybrid RF systems on printed circuit board (PCB) as a reference, the most commonly used passive components are discussed, and RF isolation techniques at chip and package level are explained.

Summary: The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is the first practical bandgap-engineered device to be realized in silicon. This course will provide a comprehensive review of the state-of-the-art in SiGe HBTs and assess its potential for current and future wireless and wireline applications. SiGe HBT technology combines transistor performance competitive with III-V technologies such as GaAs and InP with the processing maturity, integration levels, yield, and cost commonly associated with conventional Si CMOS fabrication. First-generation SiGe HBTs can deliver: fT in excess of 50 GHz, fmax in excess of 70 GHz, minimum noise figure below 0.5 dB at 2.0 GHz, linearity efficiency (OIP3/Pdc) above 10, 1/f noise corner frequencies below 1 kHz, operation at cryogenic temperatures, excellent radiation hardness, as well as yield, reliability and cost comparable to Si. Aggressively-scaled SiGe HBTs can achieve greater than 200 GHz transistor-level performance, and thus are expected to enable Si-based solutions for >40 GB/sec data links and emerging RF, microwave, and even mm-wave systems.

Summary: A chip plan of the layout will be created from the architecture and block diagram discussed in the previous tutorial. This chip plan leads to the next design steps of the array and the circuits that interface to it. A very accurate model of the memory array will be developed and put into SPICE for all of the future simulations. Array waveforms from actual SPICE simulations will be reviewed in detail with a focus on the prechage signal and the resulting precharge circuitry that must interface to the bitlines. Schematics of the precharge circuit will be presented along with a detailed discussion of the requirements and how it relates to the read cycle. Layout of the precharge circuit will be supplied along with a SPICE netlist that includes extracted parasitic capacitance from the layout.

Summary: A good design approach is to first consider the read cycle by designing the read path from the memory cell all the way out to the Data Out Pad. This tutorial takes the small signal that the memory cell creates and focuses on the Sensing Scheme that is required to create the gain necessary to create a full CMOS level. The function and design of the Sense Amp will be discussed in detail as well as the key requirements of the various control signals. Some of which have dual purposes such as controlling precharge and performing a 1 of 2 decode. There are many subtle things that must be considered and analyzed when designing the Sensing Scheme, not only in the schematics but in the layout as well. As such, portions of the layout will be reviewed along with an approach that eliminates noise that could cause it to fail. Plots of the layout will be provided along with an extracted SPICE netlist. Waveforms from the SPICE simulation will also be reviewed.

Summary: This tutorial walks you through the initial steps in designing an SRAM and then focuses on the first circuit that we must design - the memory cell. An overview of the architecture will be presented in a block diagram that will describe the functions of the major blocks required to create an SRAM. A large portion of this video will be dedicated to the design and layout of the memory cell (also called the bit cell) and how it is arrayed. It starts with a description of how the memory cell works then analyzes how the cell is read and written; with specific attention paid to read disturb which can cause the cell to inadvertently flip when it is read. Waveforms from SPICE simulations of the memory cell will be presented along with a SPICE input file that can be used to create your own simulations. A SPICE netlist from the layout of the memory cell will also be supplied so that the actual parasitic capacitance can be included in the simulations.

Summary: This course provides a clear understanding of the principles of delta-sigma (ΔΣ) converter operation-analog to digital and digital to analog. It introduces the best computer-aided analysis and design techniques available. The course uses simplified methods to illustrate complicated concepts such as spectral estimation and switched noise.

Summary: This course describes the state-of-the-art of tunable lasers, tunable laser technologies and control of tunable lasers. It also includes a brief introduction to the basics of semiconductor lasers, as well as background on DFB lasers, in particular how a grating works as a wavelength selective element in DFB and DBR lasers. Tuning mechanisms and tuning properties will be described, and the operation of modified structures with extended tuning range will be explained, including sampled gratings and super structure gratings. The properties of codirectional couplers and the use of these in tunable lasers will be discussed. Devices such as external cavity lasers, wavelength selectable lasers, and tunable VCSELs, will also be described. Throughout the course numerous examples of laser structures from the recent technical literature will be presented. Practical issues such as characterization, operation, and control of tunable lasers, as well as switching speed and reliability, will be included.

Summary: This course reviews the present-day on-chip wiring design practices and the special characteristics of on-chip lossy transmission lines. The deficiencies of present-day RC-circuit-representation-based designs and tools are highlighted through relevant examples. Guidelines are given for how to use controlled transmission line structures and design practices are discussed for best optimizing the wiring structure and design methodologies to circumvent the negative effects and best utilize the transmission line properties in the framework of improved technological advances. CAD tool development needs are explained for wire-aware chip architecture and for migrating to performance-driven routers and layout with R(f)L(f)C interconnect representation. The large, integrated chips that are including major portions of the overall system are inheriting all the problems that package designers have faced for many years. It is explained how the system-on-chip concept needs to adopt and adapt the tools, understanding, and practices used for designing chip-to-chip interconnections.

Summary: This course delves further into the present-day on-chip wiring design practices and the special characteristics of on-chip lossy transmission lines. A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties and the interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections.

Summary: As one of the few rising stars of the semiconductor industry, WLAN design is engaging more and more engineers and companies. Essential to the overall system design, is the radio design. This tutorial will introduce the various flavors of the 802.11 WLAN PHY standards (A/B/G) and describe their specifications and impact on the radio design. The possible choices for the radio architecture (direct-conversion, low-IF, super-heterodyne) are examined and their impact on the transistor-level design will be studied. The emphasis of this tutorial is on practical aspects of design for wireless LAN radios. After completing this course you should be able to develop an understanding of: What WLAN is; 802.11b/a/g radio requirements and specifications; Radio architectures for WLAN; Impact on cost and power consumption; Choice of process technology; Analog impairments; 802.11 system performance in the presence of analog impairments; Key building blocks and calibration techniques.