A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback
Hamashita, K.
Un-Ku Moon
Youn-Jae Kook
Takasuka, K.
Takeuchi, S.
Sasidhar, N.
Hanumolu, P.K.
Asahi Kasei Microdevices, Atsugi, Japan;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Sept. 2009
Volume: 44,
Issue: 9
On page(s): 2392-2401
ISSN: 0018-9200
INSPEC Accession Number: 10846954
Digital Object Identifier: 10.1109/JSSC.2009.2025408
Current Version Published: 2009-08-28
Abstract
A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 mum CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.
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