Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages
Maxey, J.
Yang, C.-K.K.
Ping-Hsuan Hsieh
Texas Instrum., Dallas, TX, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Sept. 2009
Volume: 44,
Issue: 9
On page(s): 2488-2495
ISSN: 0018-9200
INSPEC Accession Number: 10846937
Digital Object Identifier: 10.1109/JSSC.2009.2025406
Current Version Published: 2009-08-28
Abstract
A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz.
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