A 12-Bit 200-MHz CMOS ADC
Sahoo, B.D.
Razavi, B.
Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Sept. 2009
Volume: 44,
Issue: 9
On page(s): 2366-2380
ISSN: 0018-9200
INSPEC Accession Number: 10846959
Digital Object Identifier: 10.1109/JSSC.2009.2024809
Current Version Published: 2009-08-28
Abstract
A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply.
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